// Copyright (C) 1953-2022 NUDT
// Verilog module name - configuration_parse_and_encapsulate_taux_reg
// Version: V4.0.20221216
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//        configuration_parse_and_encapsulate test aux
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module configuration_parse_and_encapsulate_taux_reg
(
		i_clk,
		i_rst_n,
		
		iv_command       ,
        i_command_wr     ,        
        ov_command_ack   ,
        o_command_ack_wr ,
		
		ov_flowid_reg_rx0,
		ov_flowid_reg_rx1,
		ov_flowid_reg_rx2,
		ov_flowid_reg_rx3,
			  
		ov_flowid_reg_tx0,
		ov_flowid_reg_tx1,
		ov_flowid_reg_tx2,
		ov_flowid_reg_tx3,
	
		ov_PTO_select_reg,		
		ov_dmac,
		ov_mirror_mode  
);

input 				i_clk;
input				i_rst_n;
input		[63:0]	iv_command;		
input				i_command_wr;
output	reg	[63:0]	ov_command_ack;
output	reg			o_command_ack_wr;

output	reg	[13:0]	ov_flowid_reg_rx0;
output	reg	[13:0]	ov_flowid_reg_rx1;
output	reg	[13:0]	ov_flowid_reg_rx2;
output	reg [13:0]	ov_flowid_reg_rx3;

output	reg	[13:0]	ov_flowid_reg_tx0;
output  reg	[13:0]	ov_flowid_reg_tx1;
output  reg	[13:0]	ov_flowid_reg_tx2;
output  reg [13:0]	ov_flowid_reg_tx3;

output	reg	[6:0]	ov_PTO_select_reg;
output	reg	[47:0]	ov_dmac;
output	reg	[1:0]	ov_mirror_mode;

always@(posedge i_clk or negedge i_rst_n) begin
	if(! i_rst_n) begin
		ov_flowid_reg_rx0		<= 14'd0;
		ov_flowid_reg_rx1		<= 14'd0;
		ov_flowid_reg_rx2		<= 14'd0;
		ov_flowid_reg_rx3		<= 14'd0;		
		ov_flowid_reg_tx0		<= 14'd0;
		ov_flowid_reg_tx1		<= 14'd0;
		ov_flowid_reg_tx2		<= 14'd0;
		ov_flowid_reg_tx3		<= 14'd0;	
		ov_PTO_select_reg		<= 7'd0;
		ov_dmac					<= 48'd0;
		ov_mirror_mode			<= 2'd0;
		ov_command_ack			<= 64'b0;
		o_command_ack_wr		<= 1'b0;
	end
	else begin
		if (i_command_wr == 1'b1) begin
			if(iv_command[57:51] == 7'h0)begin //configure DIT module
				if(iv_command[63:62] == 2'h0) begin //write								
					case(iv_command[50:32])
						19'd0: ov_flowid_reg_rx0 <= iv_command[13:0];
						19'd1: ov_flowid_reg_rx1 <= iv_command[13:0];
						19'd2: ov_flowid_reg_rx2 <= iv_command[13:0];
						19'd3: ov_flowid_reg_rx3 <= iv_command[13:0];						
						19'd4: ov_flowid_reg_tx0 <= iv_command[13:0];
						19'd5: ov_flowid_reg_tx1 <= iv_command[13:0];
						19'd6: ov_flowid_reg_tx2 <= iv_command[13:0];
						19'd7: ov_flowid_reg_tx3 <= iv_command[13:0];						
						19'd8: ov_PTO_select_reg <= iv_command[6:0];											
						19'd9: ov_dmac[47:32]    <= iv_command[15:0];
						19'd10: ov_dmac[31:0]    <= iv_command[31:0];
						19'd11: ov_mirror_mode[1:0]    <= iv_command[1:0];						
						default: begin
							ov_flowid_reg_rx0	 <= ov_flowid_reg_rx0;
							ov_flowid_reg_rx1	 <= ov_flowid_reg_rx1;
							ov_flowid_reg_rx2	 <= ov_flowid_reg_rx2;
							ov_flowid_reg_rx3	 <= ov_flowid_reg_rx3;
							ov_flowid_reg_tx0	 <= ov_flowid_reg_tx0;
							ov_flowid_reg_tx1	 <= ov_flowid_reg_tx1;
							ov_flowid_reg_tx2	 <= ov_flowid_reg_tx2;
							ov_flowid_reg_tx3	 <= ov_flowid_reg_tx3;
							ov_PTO_select_reg	 <= ov_PTO_select_reg;
							ov_dmac				 <= ov_dmac			 ;
							ov_mirror_mode		 <= ov_mirror_mode	 ;
						end						
					endcase						
				end
				else if(iv_command[63:62] == 2'h2) begin //read
					if(iv_command[50:32]<19'd12)begin
						o_command_ack_wr	  <= 1'b1;
						ov_command_ack[63:62] <= 2'h3;
						ov_command_ack[61:32] <= iv_command[61:32];
				    end
					else begin
						o_command_ack_wr	  <= 1'b0;
						ov_command_ack        <= 64'h0;					
					end
					case(iv_command[50:32])
						19'd0:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_rx0}; 
						19'd1:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_rx1};
						19'd2:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_rx2};
						19'd3:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_rx3};						                             
						19'd4:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_tx0};
						19'd5:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_tx1};
						19'd6:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_tx2};
						19'd7:   ov_command_ack[31:0] <=  {18'b0,ov_flowid_reg_tx3};						                             
						19'd8:   ov_command_ack[31:0] <=  {25'b0,ov_PTO_select_reg};
						19'd9:   ov_command_ack[31:0] <=  {16'b0,ov_dmac[47:32]} ;   
						19'd10:  ov_command_ack[31:0] <=  ov_dmac[31:0]    ;  
						19'd11:  ov_command_ack[31:0] <=  {30'b0,ov_mirror_mode[1:0]} ;						                            
						default: ov_command_ack[31:0] <=  ov_command_ack[31:0];
					endcase						
				end
				else begin
					o_command_ack_wr <= 1'b0;
				end
			end 
			else begin
			o_command_ack_wr <= 1'b0;
			end	
		end
		else begin
			o_command_ack_wr <= 1'b0;
		end
	end
end



endmodule 